{"title":"异步线性管道:一种高效的最优管道算法","authors":"E. Yahya, M. Renaudin","doi":"10.1109/ICECS.2008.4675095","DOIUrl":null,"url":null,"abstract":"This paper introduces a new methodology for optimizing the performance of asynchronous-linear pipelines. The method supports all delay types, static and variable time delays, enabling the designers to optimize their architecture taking into account the timing information of data dependencies, circuit structure and process variations. The method not only determines the minimum degree of pipelining necessary to satisfy a given performance target, but also computes the optimum placement of the pipeline stages to maximize the throughput.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"35 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Asynchronous Linear Pipelines: An efficient-optimal pipelining algorithm\",\"authors\":\"E. Yahya, M. Renaudin\",\"doi\":\"10.1109/ICECS.2008.4675095\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper introduces a new methodology for optimizing the performance of asynchronous-linear pipelines. The method supports all delay types, static and variable time delays, enabling the designers to optimize their architecture taking into account the timing information of data dependencies, circuit structure and process variations. The method not only determines the minimum degree of pipelining necessary to satisfy a given performance target, but also computes the optimum placement of the pipeline stages to maximize the throughput.\",\"PeriodicalId\":404629,\"journal\":{\"name\":\"2008 15th IEEE International Conference on Electronics, Circuits and Systems\",\"volume\":\"35 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-11-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 15th IEEE International Conference on Electronics, Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICECS.2008.4675095\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECS.2008.4675095","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Asynchronous Linear Pipelines: An efficient-optimal pipelining algorithm
This paper introduces a new methodology for optimizing the performance of asynchronous-linear pipelines. The method supports all delay types, static and variable time delays, enabling the designers to optimize their architecture taking into account the timing information of data dependencies, circuit structure and process variations. The method not only determines the minimum degree of pipelining necessary to satisfy a given performance target, but also computes the optimum placement of the pipeline stages to maximize the throughput.