Notice of Violation of IEEE Publication PrinciplesA 10GHz SiGe OC192 frequency synthesizer using a passive feed-forward loop filter and a half rate oscillator

A 10 GHz OC192 PLL frequency synthesizer was realized in a 0.25 μm SiGe BiCMOS process with 60 GHz transition frequency. Its phase noise was significantly reduced by using a half rate oscillator followed by a frequency doubler that alleviates the low quality factor of junction varactors at 10 GHz. A fully integrated loop filter was implemented using a passive feed-forward configuration, in conjunction with a Miller capacitance multiplier. A process and divider modulus independent PLL architecture keeps constant the phase margin, settling time and loop sampling ratio over design corners. The IC specifications include: 9.953/10.3125 GHz serial data rates, 155/622 MHz reference frequency, 5 mUI/sub rms/ serial clock random jitter, <8ps/sub p-p/ serial data deterministic jitter, 120 dBc oscillator phase noise at 100 kHz offset, 3-3.6 supply voltage, 1 W power dissipation and 2×2 mm/sup 2/ die area.