Yu Li, Fei Chen, Dang Liu, Xiaoyong Li, Yang Li, Yudong Zhang, Zhicheng Wang, W. Rhee, Zhihua Wang
{"title":"基于0.18μm CMOS的1.6Mb/s 3.75-4.25GHz啁啾超宽带收发器","authors":"Yu Li, Fei Chen, Dang Liu, Xiaoyong Li, Yang Li, Yudong Zhang, Zhicheng Wang, W. Rhee, Zhihua Wang","doi":"10.1109/RFIT.2014.6933254","DOIUrl":null,"url":null,"abstract":"A chirp-UWB transceiver which transmits a 1.3 bit information in a single pulse clock period by embedding pulse position information in the chirp FSK modulation is implemented in 0.18μm CMOS. A digital-intensive chirp-UWB transmitter by employing digital ramp generator and a digitally-controlled oscillator (DCO) is designed. In the receiver, a dual-BPF based regenerative architecture is employed to relax the Q requirement. The proposed transceiver achieves the energy efficiency of 2.5nJ/b for the transmitter and 24.2nJ/b for the receiver at the data rate of 1.6Mb/s.","PeriodicalId":281858,"journal":{"name":"2014 IEEE International Symposium on Radio-Frequency Integration Technology","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A 1.6Mb/s 3.75–4.25GHz chirp-UWB transceiver with enhanced spectral efficiency in 0.18μm CMOS\",\"authors\":\"Yu Li, Fei Chen, Dang Liu, Xiaoyong Li, Yang Li, Yudong Zhang, Zhicheng Wang, W. Rhee, Zhihua Wang\",\"doi\":\"10.1109/RFIT.2014.6933254\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A chirp-UWB transceiver which transmits a 1.3 bit information in a single pulse clock period by embedding pulse position information in the chirp FSK modulation is implemented in 0.18μm CMOS. A digital-intensive chirp-UWB transmitter by employing digital ramp generator and a digitally-controlled oscillator (DCO) is designed. In the receiver, a dual-BPF based regenerative architecture is employed to relax the Q requirement. The proposed transceiver achieves the energy efficiency of 2.5nJ/b for the transmitter and 24.2nJ/b for the receiver at the data rate of 1.6Mb/s.\",\"PeriodicalId\":281858,\"journal\":{\"name\":\"2014 IEEE International Symposium on Radio-Frequency Integration Technology\",\"volume\":\"6 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-10-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 IEEE International Symposium on Radio-Frequency Integration Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RFIT.2014.6933254\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 IEEE International Symposium on Radio-Frequency Integration Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RFIT.2014.6933254","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 1.6Mb/s 3.75–4.25GHz chirp-UWB transceiver with enhanced spectral efficiency in 0.18μm CMOS
A chirp-UWB transceiver which transmits a 1.3 bit information in a single pulse clock period by embedding pulse position information in the chirp FSK modulation is implemented in 0.18μm CMOS. A digital-intensive chirp-UWB transmitter by employing digital ramp generator and a digitally-controlled oscillator (DCO) is designed. In the receiver, a dual-BPF based regenerative architecture is employed to relax the Q requirement. The proposed transceiver achieves the energy efficiency of 2.5nJ/b for the transmitter and 24.2nJ/b for the receiver at the data rate of 1.6Mb/s.