一种新型的用户友好的FPGA设计逻辑加密自动化框架

2020 IEEE 17th International Conference on Smart Communities: Improving Quality of Life Using ICT, IoT and AI (HONET) Pub Date : 2020-12-14 DOI:10.1109/HONET50430.2020.9322831

William J. Halaburda, Guillermo Briceno, Wallace Obey, Nabila BouSaba, F. Saqib

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引用次数: 0

摘要

硬件安全在现代集成电路和FPGA设计工具链中已经成为一个次要问题。开发了一种FPGA设计逻辑加密的自动化框架，该框架集成了多种设计锁定技术，将IP和用户保护置于芯片设计的预先考虑之中。

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A Novel User-Friendly Automated Framework for FPGA Design Logic Encryption

Hardware security has become an afterthought in the modern IC and FPGA design toolchain. An automated framework for FPGA design logic encryption has been developed that integrates multiple design locking techniques to place IP and user protection at the forethought of chip design.

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来源期刊

2020 IEEE 17th International Conference on Smart Communities: Improving Quality of Life Using ICT, IoT and AI (HONET)

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