双mos:双mos栅极的基本单元

1989 Proceedings of the IEEE Custom Integrated Circuits Conference Pub Date : 1989-05-15 DOI:10.1109/CICC.1989.56710

A. El Gamal, J. Kouloheris, D. How, M. Morf

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引用次数: 54

摘要

采用0.8 μm BiCMOS技术设计并制作了BiNMOS测试芯片。测试芯片由4×22 BiNMOS单元阵列组成。测试结构包括一个环形振荡器，一个4位SRAM(静态随机存取存储器)核心，五种类型的缓冲器，一个MUX和一个移位寄存器。环形振荡器测量表明，基本的BiNMOS逆变器延迟为240 ps (FO=1)，结果与仿真结果吻合良好

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BiNMOS: a basic cell for BiCMOS sea-of-gates

A BiNMOS test chip has been designed and fabricated in 0.8-μm BiCMOS technology. The test chip consists of a 4×22 array of BiNMOS cells. The test structures include a ring oscillator, a 4-bit SRAM (static random-access memory) core, five types of buffers, a MUX, and a shift register. Ring oscillator measurements indicate a basic BiNMOS inverter delay of 240 ps (FO=1), a result that agrees well with simulation

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1989 Proceedings of the IEEE Custom Integrated Circuits Conference

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