基于SOI PowerPC7448的DMT和DT2容错体系结构验证测试平台的开发

2008 14th IEEE International On-Line Testing Symposium Pub Date : 2008-07-07 DOI:10.1109/IOLTS.2008.24

M. Pignol, Thierry Parrain, Vincent Claverie, C. Boléat, G. Estaves

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引用次数: 4

摘要

在法国空间研究中心进行的TAFT容错研究的目的是使空间界为与使用COTS组件开发航天器超级计算机有关的重大演变做好准备。CNES已经获得了DMT和DT2容错架构的专利，这些架构具有“轻量级”特性。本文介绍了基于e2v公司PowerPC7448微处理器的DMT/DT2试验台的开发。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Development of a Testbench for Validation of DMT and DT2 Fault-Tolerant Architectures on SOI PowerPC7448

The purpose of TAFT fault tolerance studies conducted at CNES is to prepare the space community for the significant evolution linked to the usage of COTS components for developing spacecraft supercomputers. CNES has patented the DMT and DT2 fault-tolerant architectures with 'light' features. The development of a DMT/DT2 testbench based on a PowerPC7448 microprocessor from e2v is presented in this paper.

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2008 14th IEEE International On-Line Testing Symposium

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