T. L. Tan, P. Zhou, L. Cao, P. Tan, P. Paliwoda, C. Eng
{"title":"门通比设计的可靠性","authors":"T. L. Tan, P. Zhou, L. Cao, P. Tan, P. Paliwoda, C. Eng","doi":"10.1109/IIRW.2018.8727091","DOIUrl":null,"url":null,"abstract":"Plasma induced charging is known to cause gate oxide and MIM capacitor reliability degradation. However, the impact of plasma induced charging on metal/via is rarely reported. This paper highlights the importance of built-in-reliability during design of via connections to gate poly. Large gate oxide area per via is shown to impact via resistance and reliability. Thus, it is recommended to ground these via or design gate oxide area per via to be less than 600 $u {\\mathrm{ m}}^{\\mathbf {2}}$ to minimize the impact.","PeriodicalId":365267,"journal":{"name":"2018 International Integrated Reliability Workshop (IIRW)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Gate-to-via ratio design for reliability\",\"authors\":\"T. L. Tan, P. Zhou, L. Cao, P. Tan, P. Paliwoda, C. Eng\",\"doi\":\"10.1109/IIRW.2018.8727091\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Plasma induced charging is known to cause gate oxide and MIM capacitor reliability degradation. However, the impact of plasma induced charging on metal/via is rarely reported. This paper highlights the importance of built-in-reliability during design of via connections to gate poly. Large gate oxide area per via is shown to impact via resistance and reliability. Thus, it is recommended to ground these via or design gate oxide area per via to be less than 600 $u {\\\\mathrm{ m}}^{\\\\mathbf {2}}$ to minimize the impact.\",\"PeriodicalId\":365267,\"journal\":{\"name\":\"2018 International Integrated Reliability Workshop (IIRW)\",\"volume\":\"64 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 International Integrated Reliability Workshop (IIRW)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IIRW.2018.8727091\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 International Integrated Reliability Workshop (IIRW)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IIRW.2018.8727091","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Plasma induced charging is known to cause gate oxide and MIM capacitor reliability degradation. However, the impact of plasma induced charging on metal/via is rarely reported. This paper highlights the importance of built-in-reliability during design of via connections to gate poly. Large gate oxide area per via is shown to impact via resistance and reliability. Thus, it is recommended to ground these via or design gate oxide area per via to be less than 600 $u {\mathrm{ m}}^{\mathbf {2}}$ to minimize the impact.
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