一种用于晶圆级集成的高性能单片FFT阵列处理器

1990 Proceedings. International Conference on Wafer Scale Integration Pub Date : 1990-01-23 DOI:10.1109/ICWSI.1990.63884

Jaehee You, S.S. Wong

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引用次数: 5

摘要

为了实现基数p的FFT，我们设计了一个每蝶级有p个乘法器和加法器的结构。它是基于基数p的p-fold对称常数几何FFT算法。提出了一种用低基数硬件实现高基数处理单元的方法。适用于晶圆规模的集成。评估了该体系结构的延迟和吞吐量。在CMOS上成功地设计了一个实现2,8点FFT的实验处理器芯片，并对结果进行了讨论。

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A high performance single chip FFT array processor for wafer scale integration

An architecture with p multiplier-adder's per butterfly stage has been developed to implement a radix p FFT. It is based on the p-fold symmetry in radix p constant geometry FFT algorithm. A methodology to realize a high radix processing element with lower radix hardware is presented. It is suitable for wafer scale integration. The latency and throughput of this architecture are evaluated. An experimental processor chip to implement a radix 2, 8 point FFT has been successfully designed in CMOS and the results are discussed.<>

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1990 Proceedings. International Conference on Wafer Scale Integration

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