A new 2-D parity checking architecture for radiation-hardened by design SRAM

A novel tow-dimension (2-D) parity checking architecture is proposed for Radiation-Hardened by Design (RHBD) SRAMs, which are insensitive to radiation-induced single-event upsets (SEU). The common 2-D parity checking method and its limitations in high density RHBD SRAMs are discussed. The novel architecture, which could be used to correct up to four adjacent upset errors, is more suitable for protecting high density memories from SEU. This novel 2-D parity checking architecture has been successfully used in RHBD SRAMs embedded in a SOC chip.