次太赫兹CMOS探测器阵列的测试与配置架构

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI:10.1109/DDECS.2012.6219033

P. Földesy, D. Gergelyi, C. Fuzy, G. Károlyi

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引用次数: 6

摘要

本文介绍了一种90 nm CMOS亚太赫兹探测器阵列专用集成电路的结构和可测试性问题。亚太赫兹探测器阵列是由硅场效应等离子体波传感器、集成天线、前置放大器、adc和数字域锁定放大器探测器组成的集成系统。混合信号系统由JTAG接口控制和监控，该接口包含多个接入点和多个电源域。峰值响应率为185 kV/W@365 GHz，最大探测率为20 pW/Hz-1。

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Test and configuration architecture of a sub-THz CMOS detector array

This paper describes the architecture and testability issues of a 90 nm CMOS sub-THz detector array ASIC. The sub-THz detector array is an integrated system composed of silicon field effect plasma wave sensors, integrated antennas, pre-amplifiers, ADCs, and digital domain lock-in amplifier detector. The mixed-signal system is controlled and monitored by JTAG interface containing several access points and multiple power domains. The peak responsivity is found 185 kV/W@365 GHz and at the detectivity maximum the NEP ~ 20 pW/Hz-1.

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来源期刊

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)

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