从Quartus到VPR:用泰坦流将HDL转换为bif

2013 23rd International Conference on Field programmable Logic and Applications Pub Date : 2013-10-24 DOI:10.1109/FPL.2013.6645626

Kevin E. Murray, S. Whitty, Suya Liu, J. Luu, Vaughn Betz

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引用次数: 5

摘要

真实的基准测试对于FPGA架构和CAD评估非常重要。本文提供了一个演示，说明如何使用Titan流将HDL描述的设计转换为bif，并用于学术CAD工具。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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From Quartus to VPR: Converting HDL to BLIF with the Titan flow

Realistic benchmarks are important for FPGA Architecture and CAD evaluation. This paper provides a demo illustrating how designs described in HDL can be converted to BLIF using the Titan flow, and used in academic CAD tools.

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2013 23rd International Conference on Field programmable Logic and Applications

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