一种全差分、垂直结构和补偿的分差A/ d转换器

Conference Proceedings. 10th Anniversary. IMTC/94. Advanced Technologies in I & M. 1994 IEEE Instrumentation and Measurement Technolgy Conference (Cat. No.94CH3424-9) Pub Date : 1994-05-10 DOI:10.1109/IMTC.1994.351966

P. Low

{"title":"一种全差分、垂直结构和补偿的分差A/ d转换器","authors":"P. Low","doi":"10.1109/IMTC.1994.351966","DOIUrl":null,"url":null,"abstract":"This paper introduces the design of a vertically structured subranging A/D-Converter. The vertically structured analog subranging circuits combined with the most common flash ADC led to the development of a converter for high conversion rates up to a resolution of 12 Bit. The compensation of the analog circuits reduces linearity errors to a minimum. Special attention has been paid on the differential architecture of the analog subranging circuits. The major advantage of this architecture is the improvement of the SNR and the reduction of errors caused by symmetrical parasitic impedances. New results are presented with a hybrid test circuit for a 10 Bit 30 Ms/s converter.<<ETX>>","PeriodicalId":231484,"journal":{"name":"Conference Proceedings. 10th Anniversary. IMTC/94. Advanced Technologies in I & M. 1994 IEEE Instrumentation and Measurement Technolgy Conference (Cat. No.94CH3424-9)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A fully differential, vertically structured and compensated subranging A/D-converter\",\"authors\":\"P. Low\",\"doi\":\"10.1109/IMTC.1994.351966\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper introduces the design of a vertically structured subranging A/D-Converter. The vertically structured analog subranging circuits combined with the most common flash ADC led to the development of a converter for high conversion rates up to a resolution of 12 Bit. The compensation of the analog circuits reduces linearity errors to a minimum. Special attention has been paid on the differential architecture of the analog subranging circuits. The major advantage of this architecture is the improvement of the SNR and the reduction of errors caused by symmetrical parasitic impedances. New results are presented with a hybrid test circuit for a 10 Bit 30 Ms/s converter.<<ETX>>\",\"PeriodicalId\":231484,\"journal\":{\"name\":\"Conference Proceedings. 10th Anniversary. IMTC/94. Advanced Technologies in I & M. 1994 IEEE Instrumentation and Measurement Technolgy Conference (Cat. No.94CH3424-9)\",\"volume\":\"29 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-05-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Conference Proceedings. 10th Anniversary. IMTC/94. Advanced Technologies in I & M. 1994 IEEE Instrumentation and Measurement Technolgy Conference (Cat. No.94CH3424-9)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IMTC.1994.351966\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Conference Proceedings. 10th Anniversary. IMTC/94. Advanced Technologies in I & M. 1994 IEEE Instrumentation and Measurement Technolgy Conference (Cat. No.94CH3424-9)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IMTC.1994.351966","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

本文介绍了一种垂直结构分位a / d转换器的设计。垂直结构的模拟分位电路与最常见的闪存ADC相结合，导致了高转换率转换器的发展，最高可达12位分辨率。模拟电路的补偿将线性误差降低到最小。特别注意了模拟子交换电路的差分结构。这种结构的主要优点是提高了信噪比，减少了由对称寄生阻抗引起的误差。本文给出了一个10位30ms /s转换器的混合测试电路的新结果。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A fully differential, vertically structured and compensated subranging A/D-converter

This paper introduces the design of a vertically structured subranging A/D-Converter. The vertically structured analog subranging circuits combined with the most common flash ADC led to the development of a converter for high conversion rates up to a resolution of 12 Bit. The compensation of the analog circuits reduces linearity errors to a minimum. Special attention has been paid on the differential architecture of the analog subranging circuits. The major advantage of this architecture is the improvement of the SNR and the reduction of errors caused by symmetrical parasitic impedances. New results are presented with a hybrid test circuit for a 10 Bit 30 Ms/s converter.<>

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Conference Proceedings. 10th Anniversary. IMTC/94. Advanced Technologies in I & M. 1994 IEEE Instrumentation and Measurement Technolgy Conference (Cat. No.94CH3424-9)

自引率

0.00%

发文量