f/sub MAX/ > 500 GHz的平面化InP/InGaAs异质结双极晶体管

Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC. Pub Date : 2004-06-21 DOI:10.1109/DRC.2004.1367903

D. Sawdai, P. C. Chang, Vincent Gambin, X. Zeng, J. Yamamoto, K. Loi, G. Leslie, Michael E. Barsky, A. Gutierrez-Aitken, A. Oki

{"title":"f/sub MAX/ > 500 GHz的平面化InP/InGaAs异质结双极晶体管","authors":"D. Sawdai, P. C. Chang, Vincent Gambin, X. Zeng, J. Yamamoto, K. Loi, G. Leslie, Michael E. Barsky, A. Gutierrez-Aitken, A. Oki","doi":"10.1109/DRC.2004.1367903","DOIUrl":null,"url":null,"abstract":"To meet the demands for next generation high-speed electronics, the InP-based heterojunction bipolar transistor (HBT) must be scaled vertically to minimize transit times, scaled laterally to minimize the emitter width (W/sub E/) and the base-collector junction capacitance (C/sub BC/), and fabricated with high yield to support large circuits. Lateral scaling can involve a variety of processing techniques. In this work, we developed a dielectric planarization process which enabled aggressive scaling of both W/sub E/ and C/sub BC/ using production I-line lithography, resulting in emitters as small as 0.14 /spl mu/m, unity gain cutoff frequency (f/sub T/) up to 290 GHz, and maximum oscillation frequency (f/sub MAX/) greater than 500 GHz.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"64 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Planarized InP/InGaAs heterojunction bipolar transistors with f/sub MAX/ > 500 GHz\",\"authors\":\"D. Sawdai, P. C. Chang, Vincent Gambin, X. Zeng, J. Yamamoto, K. Loi, G. Leslie, Michael E. Barsky, A. Gutierrez-Aitken, A. Oki\",\"doi\":\"10.1109/DRC.2004.1367903\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"To meet the demands for next generation high-speed electronics, the InP-based heterojunction bipolar transistor (HBT) must be scaled vertically to minimize transit times, scaled laterally to minimize the emitter width (W/sub E/) and the base-collector junction capacitance (C/sub BC/), and fabricated with high yield to support large circuits. Lateral scaling can involve a variety of processing techniques. In this work, we developed a dielectric planarization process which enabled aggressive scaling of both W/sub E/ and C/sub BC/ using production I-line lithography, resulting in emitters as small as 0.14 /spl mu/m, unity gain cutoff frequency (f/sub T/) up to 290 GHz, and maximum oscillation frequency (f/sub MAX/) greater than 500 GHz.\",\"PeriodicalId\":385948,\"journal\":{\"name\":\"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.\",\"volume\":\"64 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-06-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DRC.2004.1367903\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DRC.2004.1367903","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

摘要

为了满足下一代高速电子产品的需求，基于inp的异质结双极晶体管(HBT)必须垂直缩放以最小化传输时间，横向缩放以最小化发射极宽度(W/sub E/)和基极-集电极结电容(C/sub BC/)，并以高成品率制造以支持大型电路。横向缩放可以涉及多种处理技术。在这项工作中，我们开发了一种介质平面化工艺，可以使用生产线光刻技术对W/sub E/和C/sub BC/进行大规模缩放，从而使发射器小至0.14 /spl mu/m，单位增益截止频率(f/sub T/)高达290 GHz，最大振荡频率(f/sub MAX/)大于500 GHz。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Planarized InP/InGaAs heterojunction bipolar transistors with f/sub MAX/ > 500 GHz

To meet the demands for next generation high-speed electronics, the InP-based heterojunction bipolar transistor (HBT) must be scaled vertically to minimize transit times, scaled laterally to minimize the emitter width (W/sub E/) and the base-collector junction capacitance (C/sub BC/), and fabricated with high yield to support large circuits. Lateral scaling can involve a variety of processing techniques. In this work, we developed a dielectric planarization process which enabled aggressive scaling of both W/sub E/ and C/sub BC/ using production I-line lithography, resulting in emitters as small as 0.14 /spl mu/m, unity gain cutoff frequency (f/sub T/) up to 290 GHz, and maximum oscillation frequency (f/sub MAX/) greater than 500 GHz.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.

自引率

0.00%

发文量