Discrete Cosine Transform Hardware Accelerator in Parallel Ultra-low Power System

In this paper, the architecture of a fully pipelined discrete cosine transform ( DCT) hardware accelerator for a JPEG encoder is proposed. The integration of the accelerator into the parallel ultra-low power (PULP) platform is also demonstrated. The accelerator architecture is divided into two one-dimensional transform cores with one transpose buffer between them . With the designed accelerator, it is possible to calculate one 2D DCT operation in 32 cycles with a latency of 80 cycles. The JPEG DCT hardware accelerator is integrated into the PULP cluster as a separate processing element (PE) and successfully implemented on the Xilinx ZC706 evaluation board. The accelerator can achieve the performance of up to 1.78M transformations per second working on the clock frequency of 57 MHz.