55nm SiGe BiCMOS的6位56 gsa /s DAC

2021 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS) Pub Date : 2021-12-05 DOI:10.1109/BCICTS50416.2021.9682204

B. Moeneclaey, M. Verplaetse, H. Ramon, N. Singh, Haolin Li, J. V. Kerrebrouck, X. Yin, G. Torfs

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引用次数: 1

摘要

我们提出了一个6位56 gsa /s数模转换器(DAC)，实现在55纳米SiGe BiCMOS。它消耗2.36 W，其中0.77 W用于DAC核心。实验表明，模拟3db带宽超过28ghz，有效比特数(ENOB)为3.9。我们演示了112 Gb/s四电平脉冲幅度调制(PAM-4)和168 Gb/s PAM-8在一个由电探针和20厘米射频电缆组成的信道上的传输。通过预均衡补偿信道损耗，我们实现了0.59 Vpp的信号摆幅。

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A 6-bit 56-GSa/s DAC in 55 nm SiGe BiCMOS

We present a 6-bit 56-GSa/s digital-to-analog converter (DAC), implemented in 55 nm SiGe BiCMOS. It consumes 2.36 W of which 0.77 W is utilized in the DAC core. Experiments show an analog 3-dB bandwidth exceeding 28 GHz and an effective number of bits (ENOB) of 3.9. We demonstrate transmission of 112 Gb/s four-level pulse-amplitude modulation (PAM-4) and 168 Gb/s PAM-8 over a channel consisting of an electrical probe and 20 cm RF cables. With pre-equalization compensating the channel loss, we achieve a 0.59 Vpp signal swing.

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2021 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)

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