s波段监视雷达脉冲压缩的设计与实现

Kalfika Yani, F. Y. Suratman, Koredianto Usman
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引用次数: 0

摘要

雷达对空监视系统由天线、射频前端、雷达信号处理和雷达数据处理4个主要部分组成。雷达信号处理从基带到中频段开始。雷达波形由两类信号组成,有连续波(CW)雷达和脉冲压缩雷达[1]。对于一个给定的雷达,距离分辨率可以通过使用非常短的脉冲显著提高。脉冲压缩使我们能够获得较长脉冲的平均发射功率,同时获得短脉冲对应的距离分辨率。脉冲压缩有压缩增益。在相同功率下,脉冲压缩雷达比连续波雷达传输信号更远。在现代雷达中,波形是在数字平台上实现的。利用数字化平台,无需开发新的硬件平台即可实现雷达波形优化。现场可编程门阵列(FPGA)具有高速数据速率和并行处理能力,是实现雷达信号处理的最佳平台。在本研究中,我们使用Xilinx ML-605 Virtex-6平台结合FMC-150高速ADC/DAC设计了从基带到中频的雷达信号处理。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Design and Implementation Pulse Compression for S-Band Surveillance Radar
The radar air surveillance system consists of 4 main parts, there are antenna, RF front-end, radar signal processing, and radar data processing. Radar signal processing starts from the baseband to IF section. The radar waveform consists of two types of signal, there are continuous wave (CW) radar, and pulse compression radar [1]. Range resolution for a given radar can be significantly improved by using very short pulses. Pulse compression allows us to achieve the average transmitted power of a relatively long pulse, while obtaining the range resolution corresponding to a short pulse. Pulse compression have compression gain. With the same power, pulse compression radar can transmit signal further than CW radar. In the modern radar, waveform is implemented in digital platform. With digital platform, the radar waveform can optimize without develop the new hardware platform. Field Programmable Gate Array (FPGA) is the best platform to implemented radar signal processing, because FPGA have ability to work in high speed data rate and parallel processing. In this research, we design radar signal processing from baseband to IF using Xilinx ML-605 Virtex-6 platform which combined with FMC-150 high speed ADC/DAC.
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