{"title":"NPU ASIC芯片测试仪","authors":"G. Ren, Ling Wang, Deyuan Gao","doi":"10.1109/ICSICT.1995.503549","DOIUrl":null,"url":null,"abstract":"NPU ASIC chip tester is a low cost, functional tester. It can test chips in three modes: off-line, on-line, interactive. It can test chips that have up to 128 pins. Each test driver of this tester is programmable independently. Its hardware is implemented mainly using Xilinx FPGAs. It has a powerful software package, which facilitates the design of test programs and the analysis of test results. This software package also provides interfaces with many current EDA tools.","PeriodicalId":286176,"journal":{"name":"Proceedings of 4th International Conference on Solid-State and IC Technology","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"NPU ASIC chip tester\",\"authors\":\"G. Ren, Ling Wang, Deyuan Gao\",\"doi\":\"10.1109/ICSICT.1995.503549\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"NPU ASIC chip tester is a low cost, functional tester. It can test chips in three modes: off-line, on-line, interactive. It can test chips that have up to 128 pins. Each test driver of this tester is programmable independently. Its hardware is implemented mainly using Xilinx FPGAs. It has a powerful software package, which facilitates the design of test programs and the analysis of test results. This software package also provides interfaces with many current EDA tools.\",\"PeriodicalId\":286176,\"journal\":{\"name\":\"Proceedings of 4th International Conference on Solid-State and IC Technology\",\"volume\":\"27 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-10-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of 4th International Conference on Solid-State and IC Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICSICT.1995.503549\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 4th International Conference on Solid-State and IC Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSICT.1995.503549","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
NPU ASIC chip tester is a low cost, functional tester. It can test chips in three modes: off-line, on-line, interactive. It can test chips that have up to 128 pins. Each test driver of this tester is programmable independently. Its hardware is implemented mainly using Xilinx FPGAs. It has a powerful software package, which facilitates the design of test programs and the analysis of test results. This software package also provides interfaces with many current EDA tools.
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