Vassilis Alimisis, Marios Gourdouparis, Christos Dimas, P. Sotiriadis
{"title":"用电流反馈运算放大器实现镍镉电池分数阶模型","authors":"Vassilis Alimisis, Marios Gourdouparis, Christos Dimas, P. Sotiriadis","doi":"10.1109/ECCTD49232.2020.9218311","DOIUrl":null,"url":null,"abstract":"This work proposes an integrated-circuit architecture emulating a standard fractional-order model of NickelCadmium cell for computer simulating electrochemical behavior. The architecture is based on fractional-order elements implemented with both active and passive components, offering an accurate transfer function behavior up to 250Hz. It consists of a reduced number of active elements and implements analog allpass filters coupled with a current conveyor. Performance and accuracy of the proposed architecture is confirmed via Monte-Carlo analysis. The proposed circuitry has been designed in TSMC 90nm CMOS process and simulated using the Cadence IC suite.","PeriodicalId":336302,"journal":{"name":"2020 European Conference on Circuit Theory and Design (ECCTD)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Implementation of Fractional-order Model of Nickel-Cadmium Cell using Current Feedback Operational Amplifiers\",\"authors\":\"Vassilis Alimisis, Marios Gourdouparis, Christos Dimas, P. Sotiriadis\",\"doi\":\"10.1109/ECCTD49232.2020.9218311\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This work proposes an integrated-circuit architecture emulating a standard fractional-order model of NickelCadmium cell for computer simulating electrochemical behavior. The architecture is based on fractional-order elements implemented with both active and passive components, offering an accurate transfer function behavior up to 250Hz. It consists of a reduced number of active elements and implements analog allpass filters coupled with a current conveyor. Performance and accuracy of the proposed architecture is confirmed via Monte-Carlo analysis. The proposed circuitry has been designed in TSMC 90nm CMOS process and simulated using the Cadence IC suite.\",\"PeriodicalId\":336302,\"journal\":{\"name\":\"2020 European Conference on Circuit Theory and Design (ECCTD)\",\"volume\":\"10 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 European Conference on Circuit Theory and Design (ECCTD)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ECCTD49232.2020.9218311\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 European Conference on Circuit Theory and Design (ECCTD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECCTD49232.2020.9218311","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Implementation of Fractional-order Model of Nickel-Cadmium Cell using Current Feedback Operational Amplifiers
This work proposes an integrated-circuit architecture emulating a standard fractional-order model of NickelCadmium cell for computer simulating electrochemical behavior. The architecture is based on fractional-order elements implemented with both active and passive components, offering an accurate transfer function behavior up to 250Hz. It consists of a reduced number of active elements and implements analog allpass filters coupled with a current conveyor. Performance and accuracy of the proposed architecture is confirmed via Monte-Carlo analysis. The proposed circuitry has been designed in TSMC 90nm CMOS process and simulated using the Cadence IC suite.