用于sro接收机的高速,高转换增益射频包络检测器

Ximing Fu, K. El-Sankary, Jianjun J. Zhou
{"title":"用于sro接收机的高速,高转换增益射频包络检测器","authors":"Ximing Fu, K. El-Sankary, Jianjun J. Zhou","doi":"10.1109/MWSCAS.2019.8884942","DOIUrl":null,"url":null,"abstract":"A high speed and high conversion gain envelope detector (ED) is designed for RF super-regenerative-oscillator (SRO) receivers. To reduce glitches from RC filtering used for common mode signal rejection, the proposed ED is implemented using a band-pass buffer as a first stage. To avoid introducing excessive time delay and maintain good performance under high data rate, the proposed design introduces back-to-back inverters operating in linear mode to enhance the conversion gain while reducing the settling time. Simulation results using 0.18um CMOS technology shows that the proposed ED achieves a high data rate of 6.66Mbps while consuming 8.45μW.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A high speed, high conversion gain RF envelope detector for SRO-receivers\",\"authors\":\"Ximing Fu, K. El-Sankary, Jianjun J. Zhou\",\"doi\":\"10.1109/MWSCAS.2019.8884942\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A high speed and high conversion gain envelope detector (ED) is designed for RF super-regenerative-oscillator (SRO) receivers. To reduce glitches from RC filtering used for common mode signal rejection, the proposed ED is implemented using a band-pass buffer as a first stage. To avoid introducing excessive time delay and maintain good performance under high data rate, the proposed design introduces back-to-back inverters operating in linear mode to enhance the conversion gain while reducing the settling time. Simulation results using 0.18um CMOS technology shows that the proposed ED achieves a high data rate of 6.66Mbps while consuming 8.45μW.\",\"PeriodicalId\":287815,\"journal\":{\"name\":\"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)\",\"volume\":\"12 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MWSCAS.2019.8884942\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.2019.8884942","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

摘要

为射频超再生振荡器(SRO)接收机设计了一种高速、高转换增益包络检测器(ED)。为了减少用于共模信号抑制的RC滤波产生的小故障,所提出的ED采用带通缓冲器作为第一阶段来实现。为了避免引入过多的时间延迟,并在高数据速率下保持良好的性能,本设计引入线性模式的背对背逆变器,以提高转换增益,同时减少稳定时间。采用0.18um CMOS技术的仿真结果表明,该器件在8.45μW的功耗下实现了6.66Mbps的高数据速率。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A high speed, high conversion gain RF envelope detector for SRO-receivers
A high speed and high conversion gain envelope detector (ED) is designed for RF super-regenerative-oscillator (SRO) receivers. To reduce glitches from RC filtering used for common mode signal rejection, the proposed ED is implemented using a band-pass buffer as a first stage. To avoid introducing excessive time delay and maintain good performance under high data rate, the proposed design introduces back-to-back inverters operating in linear mode to enhance the conversion gain while reducing the settling time. Simulation results using 0.18um CMOS technology shows that the proposed ED achieves a high data rate of 6.66Mbps while consuming 8.45μW.
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