A New Technique of Designing Low Power, Low Voltage MOS CML Circuits by using Modifications in the PDN

MOS Current Mode Logic (MCML) circuits are the basic elements in the designing of the logic gates and flip flops which are further used in designing of various digital circuits like memory, clock circuits, and registers. On the chips that involve mixed signal circuits, MCML logic circuits are highly preferred. In this paper, MCML circuits with low power consumption have been proposed by modifying the pull down network of the circuit. In the circuits, the Floating Gate Mosfet (FGMOS) and Dynamic Threshold Mosfet (DTMOS) transistors are used in place of the conventional MOS circuits. The FGMOS and DTMOS have modifiable threshold levels. Utilizing this property of the FGMOS and DTMOS, they have been employed in the CML circuits to lower the minimum voltage requirements and also the reduction of power consumption by FGMOS, using 180 nm Complementary Mosfet (CMOS) process parameters. The SPICE simulations are performed and the analysis is done for all the three circuits and the comparisons are drawn. We observe a lower supply voltage requirement in the proposed circuits and the power consumption is decreased by 30% in the FGMOS circuit, making it more suitable for low power circuits.