模拟研究了氧化物厚度变化和衬底掺杂对MOSFET中DIBL的影响

2012 5th International Conference on Computers and Devices for Communication (CODEC) Pub Date : 2012-12-01 DOI:10.1109/CODEC.2012.6509251

S. Das, S. Kundu

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引用次数: 2

摘要

本文研究了漏极诱导势垒降低与氧化物厚度和衬底掺杂的关系。利用TCAD Sentaurus工具包进行了仿真验证。采用高k介电材料代替SiO2。研究了衬底掺杂变化对漏极势垒降低的影响。

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Simulation to study the effect of variation of oxide thickness and substrate doping on DIBL in MOSFET

In this work, the Drain Induced Barrier Lowering is studied as the function of oxide thickness and substrate doping. The effects are verified simulating with TCAD Sentaurus toolkit. High-K dielectric material is used in place of SiO2. Also investigation of the effect of change in substrate doping on Drain Induced Barrier Lowering is studied.

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2012 5th International Conference on Computers and Devices for Communication (CODEC)

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