A New Generation 700 V BCD Technology that Integrates Quadruple-RESURF LDMOS with Best-in-Class Specific On-Resistance

A new generation 700 V Bipolar-CMOS-DMOS (BCD) technology is reported in this work, which integrates quadruple-RESURF LDMOS with best-in-class specific on-resistance ($R_{\text{on},\text{sp}}$). By introducing PNPN layer in the drift region to locally increase the doping concentration of deep N-type well (DNW) and provide lower on-resistance conduction paths, the quadruple-RESURF LDMOS with PNPN layer (PNPN LDMOS) can achieve low $R_{\text{on},\text{sp}}$ of 62.5 m Ω.cm2 and high breakdown voltage (BV) of 739 V, whose $R_{\text{on},\text{sp}}$ is 40.8% lower than that of the mass-produced triple-RESURF LDMOS. The corresponding analytical silicon limit of PNPN LDMOS is derived as $R_{\text{on},\text{sp}}= 5.93\times 10^{-6}\times 153\times BV^{l.67}$, which is well verified by simulated and measured results at 500 to 700 V breakdown level. Besides, parasitic or independent JFET with competitive saturation drain current ($I_{\text{Dsat}}$) is also fabricated in the BCD technology. The measured results indicate that the fabricated JFET can achieve competitive $I_{\text{Dsat}}$ of 66.5 µA/µm.