{"title":"混合信号集成电路中电流平衡逻辑的增强技术","authors":"Li Yang, J. Yuan","doi":"10.1109/ISVLSI.2003.1183499","DOIUrl":null,"url":null,"abstract":"In this paper, dual-V/sub T/ and negative feedback are proposed to reduce the noise of the current-balanced logic for mixed-signal ICs. Based on the circuit analysis and SPICE simulation, the dual-V/sub T/ technique shows advantages over the conventional current-balanced logic design in gate area, delay, power dissipation, and switching noise. The negative feedback further reduces the noise spike.","PeriodicalId":299309,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.","volume":"37 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Enhanced techniques for current balanced logic in mixed-signal ICs\",\"authors\":\"Li Yang, J. Yuan\",\"doi\":\"10.1109/ISVLSI.2003.1183499\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, dual-V/sub T/ and negative feedback are proposed to reduce the noise of the current-balanced logic for mixed-signal ICs. Based on the circuit analysis and SPICE simulation, the dual-V/sub T/ technique shows advantages over the conventional current-balanced logic design in gate area, delay, power dissipation, and switching noise. The negative feedback further reduces the noise spike.\",\"PeriodicalId\":299309,\"journal\":{\"name\":\"IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.\",\"volume\":\"37 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2003-02-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISVLSI.2003.1183499\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISVLSI.2003.1183499","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Enhanced techniques for current balanced logic in mixed-signal ICs
In this paper, dual-V/sub T/ and negative feedback are proposed to reduce the noise of the current-balanced logic for mixed-signal ICs. Based on the circuit analysis and SPICE simulation, the dual-V/sub T/ technique shows advantages over the conventional current-balanced logic design in gate area, delay, power dissipation, and switching noise. The negative feedback further reduces the noise spike.