{"title":"一种具有GHz pwm型LO的谐波抑制下变频器","authors":"Heechai Kang, R. Gharpurey","doi":"10.1109/DCAS.2018.8620191","DOIUrl":null,"url":null,"abstract":"A harmonic rejection downconverter that employs a pulse-width modulated local oscillator (PWM-LO) signal is proposed. The approach employs current-mode operation, and significantly improves performance for narrow pulse-widths, which allows for high-frequency operation. The use of an input transconductor-cell with signal-path switches decreases the sensitivity of the harmonic rejection ratio (HRR) to harmonic power level. The design is simulated in a 65-nm CMOS technology, and shows HRRs of nearly 60-70 dB for the 3rd and 5th harmonics, with a 1 GHz LO, over a range of harmonic power levels, and rise and fall times of the PWM waveform.","PeriodicalId":320317,"journal":{"name":"2018 IEEE 13th Dallas Circuits and Systems Conference (DCAS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A Harmonic Rejection Downconverter with a GHz PWM-Based LO\",\"authors\":\"Heechai Kang, R. Gharpurey\",\"doi\":\"10.1109/DCAS.2018.8620191\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A harmonic rejection downconverter that employs a pulse-width modulated local oscillator (PWM-LO) signal is proposed. The approach employs current-mode operation, and significantly improves performance for narrow pulse-widths, which allows for high-frequency operation. The use of an input transconductor-cell with signal-path switches decreases the sensitivity of the harmonic rejection ratio (HRR) to harmonic power level. The design is simulated in a 65-nm CMOS technology, and shows HRRs of nearly 60-70 dB for the 3rd and 5th harmonics, with a 1 GHz LO, over a range of harmonic power levels, and rise and fall times of the PWM waveform.\",\"PeriodicalId\":320317,\"journal\":{\"name\":\"2018 IEEE 13th Dallas Circuits and Systems Conference (DCAS)\",\"volume\":\"26 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE 13th Dallas Circuits and Systems Conference (DCAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DCAS.2018.8620191\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE 13th Dallas Circuits and Systems Conference (DCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DCAS.2018.8620191","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Harmonic Rejection Downconverter with a GHz PWM-Based LO
A harmonic rejection downconverter that employs a pulse-width modulated local oscillator (PWM-LO) signal is proposed. The approach employs current-mode operation, and significantly improves performance for narrow pulse-widths, which allows for high-frequency operation. The use of an input transconductor-cell with signal-path switches decreases the sensitivity of the harmonic rejection ratio (HRR) to harmonic power level. The design is simulated in a 65-nm CMOS technology, and shows HRRs of nearly 60-70 dB for the 3rd and 5th harmonics, with a 1 GHz LO, over a range of harmonic power levels, and rise and fall times of the PWM waveform.
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