双端口存储器的故障模型和测试

Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231) Pub Date : 1998-04-26 DOI:10.1109/VTEST.1998.670898

A. V. Goor, S. Hamdioui

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引用次数: 44

摘要

本文研究了双端口存储器同时访问对故障建模的影响。提出了新的故障模型，并对其进行了试验。获得的测试是O(n/sup 2/)阶的，这使得它们对于较大的双端口存储器不太实用。然而，当考虑内存拓扑结构时，复杂度可以降低到O(n)。

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Fault models and tests for two-port memories

In this paper the effects of simultaneous memory access on the fault modeling for two-port memories are investigated. New fault models and their march tests are presented. The obtained tests are of order O(n/sup 2/), which makes them less practical for larger two-port memories. However, the complexity can be reduced to O(n), when the memory topology is taken into account.

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Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)

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