NMOS和CMOS的性能限制

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1984.1156715

J. Pfiester, J. Shott, J. Meindl

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引用次数: 3

摘要

一个分析MOST模型项目电路性能限制将报告。最小通道长度分别为0.14 μm和0.40μm，对应于CMOS的19ps和NMOS的103ps的逻辑门延迟。

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Performance limits of NMOS and CMOS

An analytic MOST model to project circuit performance limits will be reported. Minimum channel lengths of 0.14 and 0.40μm, corresponding to logic gate delays of 19ps for CMOS and 103ps for NMOS are predicted.

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来源期刊

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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