{"title":"用于可重构片上网络的混合交换路由器的设计与实现","authors":"Hung K. Nguyen, Xuan-Tu Tran","doi":"10.1109/ATC.2016.7764800","DOIUrl":null,"url":null,"abstract":"Network-on-Chip (NoC) has been proposed as the communication paradigm for the Ultra Large-Scale Integration System-on-Chips. One of the key factors that determine the performance and the implementation cost of a NoC is the switching scheme. In this paper, we propose and implement a hybrid switching router based on the combination of wormhole and virtual cut-through switching schemes. The router is dynamically reconfigurable to exchange between switching schemes at run-time, therefore, it achieves higher average performance than wormhole switching, while reducing the implementation cost in comparison with the virtual cut-through switching. The router has been modelled at Register Transfer Level in VHDL language and then synthesized on Xilinx Virtex-7 FPGA technology. The experimental results show that this router can guarantee reliability and reduce latency about 30.2% and increase average throughput approximately 38.9% compared with the generic router. The area and power overhead compared with the generic router are acceptable.","PeriodicalId":225413,"journal":{"name":"2016 International Conference on Advanced Technologies for Communications (ATC)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Design and implementation of a hybrid switching router for the reconfigurable Network-on-Chip\",\"authors\":\"Hung K. Nguyen, Xuan-Tu Tran\",\"doi\":\"10.1109/ATC.2016.7764800\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Network-on-Chip (NoC) has been proposed as the communication paradigm for the Ultra Large-Scale Integration System-on-Chips. One of the key factors that determine the performance and the implementation cost of a NoC is the switching scheme. In this paper, we propose and implement a hybrid switching router based on the combination of wormhole and virtual cut-through switching schemes. The router is dynamically reconfigurable to exchange between switching schemes at run-time, therefore, it achieves higher average performance than wormhole switching, while reducing the implementation cost in comparison with the virtual cut-through switching. The router has been modelled at Register Transfer Level in VHDL language and then synthesized on Xilinx Virtex-7 FPGA technology. The experimental results show that this router can guarantee reliability and reduce latency about 30.2% and increase average throughput approximately 38.9% compared with the generic router. The area and power overhead compared with the generic router are acceptable.\",\"PeriodicalId\":225413,\"journal\":{\"name\":\"2016 International Conference on Advanced Technologies for Communications (ATC)\",\"volume\":\"63 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 International Conference on Advanced Technologies for Communications (ATC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ATC.2016.7764800\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 International Conference on Advanced Technologies for Communications (ATC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ATC.2016.7764800","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design and implementation of a hybrid switching router for the reconfigurable Network-on-Chip
Network-on-Chip (NoC) has been proposed as the communication paradigm for the Ultra Large-Scale Integration System-on-Chips. One of the key factors that determine the performance and the implementation cost of a NoC is the switching scheme. In this paper, we propose and implement a hybrid switching router based on the combination of wormhole and virtual cut-through switching schemes. The router is dynamically reconfigurable to exchange between switching schemes at run-time, therefore, it achieves higher average performance than wormhole switching, while reducing the implementation cost in comparison with the virtual cut-through switching. The router has been modelled at Register Transfer Level in VHDL language and then synthesized on Xilinx Virtex-7 FPGA technology. The experimental results show that this router can guarantee reliability and reduce latency about 30.2% and increase average throughput approximately 38.9% compared with the generic router. The area and power overhead compared with the generic router are acceptable.