带可控参考电路的LVDS I/O缓冲器

Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334) Pub Date : 1997-09-07 DOI:10.1109/ASIC.1997.617028

T. Gabara, W. Fischer, W. Werner, S. Siegel, M. Kothandaraman, P. Metz, D. Gradl

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引用次数: 31

摘要

受控参考电路维持LVDS输出缓冲恒过(PVT)处理、电压供应和温度变化的输出电压电平和电流值。参考电路需要一个外部电阻，并产生两个直流控制电压，这些电压应用于所有输出缓冲器。片上电阻在0至2.4 V共模范围内保持约100 /spl ω /的严格控制阻抗。给出了1.244 Gb/s速率下的实测波形。

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LVDS I/O buffers with a controlled reference circuit

A controlled reference circuit maintains the output voltage levels and current values of an LVDS output buffer constant over (PVT) processing, voltage supply, and temperature variations. The reference circuit requires one external resistor and generates two DC control voltages which are applied to all output buffers. An on-chip resistance is described which maintains a tightly controlled impedance of approximately 100 /spl Omega/ over the common mode range of 0 to 2.4 V. A measured waveform at 1.244 Gb/s is given.

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来源期刊

Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)

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