采用体侧异质结结构的高电压32v n通道LDMOSs的增强esd性能

Jhong-Yi Lai, Wei-Jung Chen, Shen-Li Chen
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引用次数: 0

摘要

随着电子产品变得越来越轻、越来越短、越来越复杂,静电放电(ESD)对集成电路(ic)的潜在损害也越来越严重。在许多应用中,高电压会导致小型化元件产生高电场和高电流密度,从而导致电路元件的栅极氧化物击穿和集成电路的热损伤。因此,为了防止上述损害,在电子产品内部增加ESD保护电路,但保护单元的面积不能太大,否则在保护电路上花费了IC制造成本的很大一部分。在本文中,我们研究了如何利用台积电的0。s微米BCD高压工艺。本工作的样品结构均使用高压n沟道横向扩散mosfet (LDMOS),并且可以通过这种保护结构改进I/O保护元件。首先,通过在nLDMOS的体端嵌入肖特基二极管,增强了器件的ESD稳健性。肖特基二极管水平寄生在体端。由于寄生肖特基二极管位于器件体电极,因此寄生BJT能力得到增强,从而更容易触发器件的导电性。因此,新元件$\mathrm{V}_{\mathrm{t}i}$和$\mathrm{V}_{\mathrm{h}}$的值减小(由于水平寄生Schottky反向所以减小明显),使得高压ESD保护元件在ESD事件下具有更好的性能,本设计也使得$\mathrm{i} _{\mathrm{t}2}$的抗ESD容量显著提高。在body-end水平(反向)嵌入Schottky元素的情况下,最大的$\mathrm{I}_{\mathrm{t}2}$是在$\mathrm{R}\mathrm{e}\mathrm{f}_{-}8\mathrm{S}_{-}\mathrm{B}_{-}8$设备上找到的,其$\mathrm{I}_{\mathrm{t}2}$的改进上升到4。529A,与参考样本相比,显著提高了244.41%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Enhanced ESD-Capability of High-Voltage 32 V N-Channel LDMOSs with the Body-Side Hetero-Junction Structure
As electronics become lighter, shorter and more complex, the potential damage to integrated circuits (ICs) from electrostatic discharge (ESD) becomes more severe. In many applications, high voltages will result in high electric fields and high current densities in miniaturized components, which can lead to gate oxide breakdown of circuit components and thermal damage in ICs. Therefore, ESD protection circuits are added inside the electronic product in order to prevent the above damage, but the area of the protection cell should not be too large, otherwise a large proportion of the IC manufacturing cost is spent on the protection circuit. In this paper, we investigate how to improve the ESD protection of the designed high-voltage components through TSMC’s 0. 1S-micron BCD HV process. The sample structures of this work all use high-voltage N-channel laterally diffused MOSFETs (LDMOS), and the I/O protection components can be improved by this protection architecture. First, the ESD robustness of the device is enhanced by embedding a Schottky diode in the bulk end of the nLDMOS. The Schottky diode is parasitized horizontally at the body terminal. Since the parasitic Schottky diode is at the body electrode of the device, the parasitic BJT capability is enhanced, making it easier to trigger the conductivity of the device. Therefore, the new components $\mathrm{V}_{\mathrm{t}i}$ and $\mathrm{V}_{\mathrm{h}}$ values decrease (because the horizontal parasitic Schottky is reversed so the decreasing is obvious), so that the high-voltage ESD protection components have a better performance under ESD events, this design also makes the anti-ESD capacity $\mathrm{I}_{\mathrm{t}2}$ significantly increased. In the case of the body-end horizontal (reversed) embedded Schottky element, the largest $\mathrm{I}_{\mathrm{t}2}$ is found on the $\mathrm{R}\mathrm{e}\mathrm{f}_{-}8\mathrm{S}_{-}\mathrm{B}_{-}8$ device, whose $\mathrm{I}_{\mathrm{t}2}$ improvement rises up to 4. 529A, an significant increase of 244.41% was achieved as compared with the reference sample.
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