{"title":"高级需求的一致性验证","authors":"N. Gorse, E. Aboulhamid, Y. Savaria","doi":"10.1109/IWSOC.2004.29","DOIUrl":null,"url":null,"abstract":"The size of today's designs makes their validation very time consuming. To manage their complexity, an evolution towards higher levels of abstraction is mandatory. This paper addresses the automatic validation of high-level requirements. It presents an approach to cope with their modeling and conceptual validation. This methodology relies on the use of a very high level formal language for modeling requirements and on characterization of error patterns for their validation. It allows effective modeling and early detection of errors in hardware design cycles.","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"69 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Consistency validation of high-level requirements\",\"authors\":\"N. Gorse, E. Aboulhamid, Y. Savaria\",\"doi\":\"10.1109/IWSOC.2004.29\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The size of today's designs makes their validation very time consuming. To manage their complexity, an evolution towards higher levels of abstraction is mandatory. This paper addresses the automatic validation of high-level requirements. It presents an approach to cope with their modeling and conceptual validation. This methodology relies on the use of a very high level formal language for modeling requirements and on characterization of error patterns for their validation. It allows effective modeling and early detection of errors in hardware design cycles.\",\"PeriodicalId\":306688,\"journal\":{\"name\":\"4th IEEE International Workshop on System-on-Chip for Real-Time Applications\",\"volume\":\"69 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-07-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"4th IEEE International Workshop on System-on-Chip for Real-Time Applications\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IWSOC.2004.29\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IWSOC.2004.29","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The size of today's designs makes their validation very time consuming. To manage their complexity, an evolution towards higher levels of abstraction is mandatory. This paper addresses the automatic validation of high-level requirements. It presents an approach to cope with their modeling and conceptual validation. This methodology relies on the use of a very high level formal language for modeling requirements and on characterization of error patterns for their validation. It allows effective modeling and early detection of errors in hardware design cycles.