mpsoc上并行应用的性能建模

M. Lattuada, C. Pilato, Antonino Tumeo, Fabrizio Ferrandi
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引用次数: 10

摘要

本文提出了一种在多处理器嵌入式系统中自动测量任务、功能或任意部分程序性能的新技术。该技术对OpenMP描述的任务进行工具化,用于表示任务并行性,而源代码中的特殊pragmas则指示要分析的其他代码片段。注释和插装是完全与目标无关的,因此可以在不同的目标体系结构、模拟器或原型上测量相同的代码。我们在FPGA合成的单个和双LEON 3平台上验证了该方法,证明了较低的仪器开销。我们展示了如何在硬件/软件设计空间探索工具中轻松利用这种技术获得的信息,通过在单处理器原型上准确地估计并行应用程序的加速。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Performance modeling of parallel applications on MPSoCs
In this paper we present a new technique for automatically measuring the performance of tasks, functions or arbitrary parts of a program on a multiprocessor embedded system. The technique instruments the tasks described by OpenMP, used to represent the task parallelism, while ad hoc pragmas in the source indicate other pieces of code to profile. The annotations and the instrumentation are completely target-independent, so the same code can be measured on different target architectures, on simulators or on prototypes. We validate the approach on a single and on a dual LEON 3 platform synthesized on FPGA, demonstrating a low instrumentation overhead. We show how the information obtained with this technique can be easily exploited in a Hardware/Software design space exploration tool, by estimating, with good accuracy, the speed-up of a parallel application given the profiling on the single processor prototype.
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