{"title":"一种基于横杆的闪存控制器设计","authors":"Yunseok Lee, Chin-Hsien Wu","doi":"10.1109/ISNE.2015.7131972","DOIUrl":null,"url":null,"abstract":"In the paper, we will propose a crossbar-based controller design for flash memory to configure a variety of possible architectures to investigate the relationship between the controllers and the NAND flash memory chips. Furthermore, the crossbar-based control design can avoid the channel-limit problem. According to experiment results, the design can simulate a variety of possible architectures and reveal the pros and cons of different architectures.","PeriodicalId":152001,"journal":{"name":"2015 International Symposium on Next-Generation Electronics (ISNE)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A crossbar-based controller design for flash memory\",\"authors\":\"Yunseok Lee, Chin-Hsien Wu\",\"doi\":\"10.1109/ISNE.2015.7131972\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In the paper, we will propose a crossbar-based controller design for flash memory to configure a variety of possible architectures to investigate the relationship between the controllers and the NAND flash memory chips. Furthermore, the crossbar-based control design can avoid the channel-limit problem. According to experiment results, the design can simulate a variety of possible architectures and reveal the pros and cons of different architectures.\",\"PeriodicalId\":152001,\"journal\":{\"name\":\"2015 International Symposium on Next-Generation Electronics (ISNE)\",\"volume\":\"5 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-05-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 International Symposium on Next-Generation Electronics (ISNE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISNE.2015.7131972\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 International Symposium on Next-Generation Electronics (ISNE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISNE.2015.7131972","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A crossbar-based controller design for flash memory
In the paper, we will propose a crossbar-based controller design for flash memory to configure a variety of possible architectures to investigate the relationship between the controllers and the NAND flash memory chips. Furthermore, the crossbar-based control design can avoid the channel-limit problem. According to experiment results, the design can simulate a variety of possible architectures and reveal the pros and cons of different architectures.