用于嵌入式无线设备的微功率CMOS射频前端

1999 IEEE Radio Frequency Integrated Circuits Symposium (Cat No.99CH37001) Pub Date : 1999-06-13 DOI:10.1109/RFIC.1999.805230

R. Rofougaran, Tsung-Hsien Lin, F. Newberg, W. Kaiser

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引用次数: 6

摘要

受低功耗窄带无线通信系统需求的推动，首个微功耗RFIC前端采用弱反转CMOS技术设计。前端是一个低噪声放大器(LNA)和一个下变频混频器，已在标准的0.8 /spl mu/m CMOS工艺中实现。在3v电源偏置时，前端电源电流小于110 /spl mu/A，工作频率为450 MHz。前端设计中使用的高q电感采用低温共烧陶瓷技术制造。前端增益为25 dB, IP3为-15 dBm。这是迄今为止在此频率下工作的CMOS前端的最低电流消耗。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A micro-power CMOS RF front-end for embedded wireless devices

Motivated by the emerging needs for low power narrow-band wireless communication systems, the first micro-power RFIC front-end has been designed using weak inversion CMOS techniques. The front-end, a low-noise amplifier (LNA) combined with a downconversion mixer, has been implemented in a standard 0.8 /spl mu/m CMOS process. The front-end supply current is less than 110 /spl mu/A at 3 V supply bias for operation at 450 MHz. High-Q inductors, used in the front-end design, have been manufactured using low-temperature cofired ceramic technology. The front-end's gain is 25 dB with an IP3 of -15 dBm. This is the lowest current consumption reported to date for a CMOS front-end operating at this frequency.

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1999 IEEE Radio Frequency Integrated Circuits Symposium (Cat No.99CH37001)

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