带缓冲大小的旋转感知快速时钟树合成

2018 International Conference on Electronics, Information, and Communication (ICEIC) Pub Date : 1900-01-01 DOI:10.23919/ELINFOCOM.2018.8330581

M. Choi, Deokkeun Oh, Juho Kim

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引用次数: 2

摘要

时钟树合成(CTS)是芯片整体性能的关键部分。时钟树中需要插入缓冲器以防止信号退化并满足摆压约束。此外，缓冲大小可以最小化时钟树网络中的功耗和倾斜。在本文中，我们提出了基于DME的旋转感知CTS快速缓冲区插入/大小方法，以满足倾斜约束。实验结果表明，该方法与基于lp的方法相比，功耗降低13.47%，运行时间降低49.03%。

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Slew-aware fast clock tree synthesis with buffer sizing

Clock tree synthesis (CTS) is a critical part on the total performance of chip. Buffer insertion is required in clock tree to prevent signal degradation and satisfy slew constraints. Also, buffer sizing minimizes power and skew in clock tree network. In this paper, we proposed slew-aware fast buffer insertion/sizing methodology in CTS based on DME to meet the skew constraints. The experiment results show the proposed sizing method reduce about 13.47% power consumption and 49.03% runtime compared to LP-based method.

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来源期刊

2018 International Conference on Electronics, Information, and Communication (ICEIC)

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