统计时序分析在实际设计中的应用

A. Nardi, E. Tuncer, S. Naidu, A. Antonau, S. Gradinaru, Tao Lin, J. Song
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引用次数: 5

摘要

关于统计静态时序分析(SSTA)、它的动机、不同的实现以及它们的运行时/精度权衡,已经发表了大量的文献。然而,关于这种新技术在实际设计中的适用性和使用模型的文献非常有限。这项工作的重点是在实际设计中使用SSTA,以及它在传统设计流程中的实际好处和局限性。作者引入了两个新的指标来驱动优化:倾斜临界性和聚合灵敏度。在时钟树分析和正确的片上变化建模方面,证明了SSTA的实际优势。本文还讨论了利用SSTA来覆盖传统的拐角分析和驱动优化。报告了在90纳米技术上实现的三个设计的结果
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Use of Statistical Timing Analysis on Real Designs
A vast literature has been published on statistical static timing analysis (SSTA), its motivations, its different implementations and their runtime/accuracy trade-offs. However, very limited literature exists on the applicability and the usage models of this new technology on real designs. This work focuses on the use of SSTA in real designs and its practical benefits and limitations over the traditional design flow. The authors introduce two new metrics to drive the optimization: skew criticality and aggregate sensitivity. Practical benefits of SSTA are demonstrated for clock tree analysis, and correct modeling of on-chip-variations. The use of SSTA to cover the traditional corner analysis and to drive optimization is also discussed. Results are reported on three designs implemented on a 90nm technology
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