基于65nm CMOS技术的多核数字控制振荡器设计

2017 Open Conference of Electrical, Electronic and Information Sciences (eStream) Pub Date : 2017-04-27 DOI:10.1109/ESTREAM.2017.7950310

V. Macaitis, R. Navickas

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引用次数: 6

摘要

本文报道了采用65 nm射频CMOS技术设计的2.37 ~ 5.94 GHz多核CMOS LC数字控制振荡器(DCO)。三核6位开关电容阵列提供宽LC-DCO调谐范围。仿真结果表明，在1.8 V电源电压下，调谐范围为2.37 GHz ~ 5.94 GHz，整个调谐范围内的平均相位噪声值为- 135 dBc/Hz。2.37 GHz时功耗仅为24 mW。提出的LC-DCO可用于现代多标准无线应用。

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Design of multicore digitally controlled oscillator in 65 nm CMOS technology

This paper reports 2.37–5.94 GHz multicore CMOS LC Digitally-Controlled Oscillator (DCO) designed in 65 nm RF CMOS technology. The three cores of 6-bit switch capacitor array provides wide LC-DCO tuning range. With 1.8 V supply voltage, simulation results show that the tuning range is from 2.37 GHz to 5.94 GHz, while average phase noise value across the entire tuning range is −135 dBc/Hz. Power dissipation is only 24 mW at 2.37 GHz. Proposed LC-DCO can be used in modern multi-standard wireless applications.

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2017 Open Conference of Electrical, Electronic and Information Sciences (eStream)

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