基于65nm CMOS工艺的DC-110GHz连续可变衰减器

2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS) Pub Date : 2017-12-01 DOI:10.1109/EDAPS.2017.8277052

Jiamei Lv, J. Wen, Long Wang, Qingping Zhang, Yonghe Wang

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引用次数: 2

摘要

采用65nm CMOS工艺设计并制作了宽带连续可变衰减器。这款π型的单侧有三个分流场效应管，具有最先进的性能，最小插入损耗为0.13-2.48 dB，整个频段匹配良好。该衰减器在DC-110GHz范围内具有连续可控性，当电压偏置从0到1.2V不断变化时，衰减范围大于16 dB。测量还表明，在10至110GHz范围内，回波损耗大于- 22dB。芯片尺寸为340×280um2，核心面积为26×109um2。

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DC-110GHz continuous variable attenuator based on 65nm CMOS process

Continuous variable attenuator with wide bandwidth has been designed and fabricated in a 65nm CMOS process. This π-type with three shunt FETs in one side demonstrates state-of-the art performance showing a minimum insertion loss of 0.13–2.48 dB and good matching across the whole band. The attenuator has a continuous controllability from DC-110GHz with an attenuation range more than 16 dB as voltage bias changed constantly varies from 0 to 1.2V. Measurements also show return loss is greater than −22dB from 10 to 110GHz. The chip size is 340×280um2 and the core area is 26×109um2.

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2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)

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