{"title":"用于无线传感器网络的0.13-/spl mu/m CMOS超低功耗前端接收器","authors":"Wenjian Chen, T. Copani, H. Barnaby, S. Kiaei","doi":"10.1109/RFIC.2007.380843","DOIUrl":null,"url":null,"abstract":"This paper presents an ultra-low power monolithic CMOS RF receiver, consisting of current re-use common gate LNA with inductive feedback gm-boosting, and followed by balanced I/Q mixers. The receiver is fabricated in a 0.13-mum CMOS digital process operating at 2.45 GHZ. The measurement results show that the RF receiver achieves a gain of 20 dB and a noise figure of 7.5 dB at 2 MHz. Input 1-dB compression point is -19 dBm and IIP3 is -10 tlBm, with 0.4 mA total current consumption from a 1.5-V supply.","PeriodicalId":356468,"journal":{"name":"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium","volume":"4 4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"A 0.13-/spl mu/m CMOS Ultra-Low Power Front-End Receiver for Wireless Sensor Networks\",\"authors\":\"Wenjian Chen, T. Copani, H. Barnaby, S. Kiaei\",\"doi\":\"10.1109/RFIC.2007.380843\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents an ultra-low power monolithic CMOS RF receiver, consisting of current re-use common gate LNA with inductive feedback gm-boosting, and followed by balanced I/Q mixers. The receiver is fabricated in a 0.13-mum CMOS digital process operating at 2.45 GHZ. The measurement results show that the RF receiver achieves a gain of 20 dB and a noise figure of 7.5 dB at 2 MHz. Input 1-dB compression point is -19 dBm and IIP3 is -10 tlBm, with 0.4 mA total current consumption from a 1.5-V supply.\",\"PeriodicalId\":356468,\"journal\":{\"name\":\"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium\",\"volume\":\"4 4 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-06-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RFIC.2007.380843\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RFIC.2007.380843","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 0.13-/spl mu/m CMOS Ultra-Low Power Front-End Receiver for Wireless Sensor Networks
This paper presents an ultra-low power monolithic CMOS RF receiver, consisting of current re-use common gate LNA with inductive feedback gm-boosting, and followed by balanced I/Q mixers. The receiver is fabricated in a 0.13-mum CMOS digital process operating at 2.45 GHZ. The measurement results show that the RF receiver achieves a gain of 20 dB and a noise figure of 7.5 dB at 2 MHz. Input 1-dB compression point is -19 dBm and IIP3 is -10 tlBm, with 0.4 mA total current consumption from a 1.5-V supply.
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