G. J. Hu, L. Tran, P. Keshtbod, J. Segal, K. Park, T. Amin, B. Prickett, S.C. Tsao, J. Yen, E. Smith, J. Bornstein, A. Alvarez
{"title":"用于高速兆比特eprom的BiFAMOS技术","authors":"G. J. Hu, L. Tran, P. Keshtbod, J. Segal, K. Park, T. Amin, B. Prickett, S.C. Tsao, J. Yen, E. Smith, J. Bornstein, A. Alvarez","doi":"10.1109/VLSIT.1992.200637","DOIUrl":null,"url":null,"abstract":"An advanced BiCMOS floating gate avalanche MOS (BiFAMOS) technology for high-speed and high-density EPROM applications is described. It is of great interest to develop chips with access times of 20 ns or less to support 33-to-50-MHz systems without a SRAM interface. Since channel hot carrier injection is used in EPROM programming, the high-current and high-voltage programming conditions limit the size of the FET that can be used in the cell and hence the low cell current directly affects speed. A two-transistor cell has been previously introduced to overcome this speed limitation but at the expense of area. Here, BiCMOS technology is used to alleviate this speed/area tradeoff. Fast bipolar sense amplifiers and high-current NPN drivers allow very-high-speed access without a large cell current. With a 1-T cell, an access time of 12 ns was obtained on a 1-Mb EPROM, demonstrating that this 0.8- mu m BiFAMOS is capable of sub-20-ns 4M EPROMs.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"BiFAMOS technology for high speed mega-bit EPROMs\",\"authors\":\"G. J. Hu, L. Tran, P. Keshtbod, J. Segal, K. Park, T. Amin, B. Prickett, S.C. Tsao, J. Yen, E. Smith, J. Bornstein, A. Alvarez\",\"doi\":\"10.1109/VLSIT.1992.200637\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An advanced BiCMOS floating gate avalanche MOS (BiFAMOS) technology for high-speed and high-density EPROM applications is described. It is of great interest to develop chips with access times of 20 ns or less to support 33-to-50-MHz systems without a SRAM interface. Since channel hot carrier injection is used in EPROM programming, the high-current and high-voltage programming conditions limit the size of the FET that can be used in the cell and hence the low cell current directly affects speed. A two-transistor cell has been previously introduced to overcome this speed limitation but at the expense of area. Here, BiCMOS technology is used to alleviate this speed/area tradeoff. Fast bipolar sense amplifiers and high-current NPN drivers allow very-high-speed access without a large cell current. With a 1-T cell, an access time of 12 ns was obtained on a 1-Mb EPROM, demonstrating that this 0.8- mu m BiFAMOS is capable of sub-20-ns 4M EPROMs.<<ETX>>\",\"PeriodicalId\":404756,\"journal\":{\"name\":\"1992 Symposium on VLSI Technology Digest of Technical Papers\",\"volume\":\"23 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-06-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1992 Symposium on VLSI Technology Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.1992.200637\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1992 Symposium on VLSI Technology Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.1992.200637","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An advanced BiCMOS floating gate avalanche MOS (BiFAMOS) technology for high-speed and high-density EPROM applications is described. It is of great interest to develop chips with access times of 20 ns or less to support 33-to-50-MHz systems without a SRAM interface. Since channel hot carrier injection is used in EPROM programming, the high-current and high-voltage programming conditions limit the size of the FET that can be used in the cell and hence the low cell current directly affects speed. A two-transistor cell has been previously introduced to overcome this speed limitation but at the expense of area. Here, BiCMOS technology is used to alleviate this speed/area tradeoff. Fast bipolar sense amplifiers and high-current NPN drivers allow very-high-speed access without a large cell current. With a 1-T cell, an access time of 12 ns was obtained on a 1-Mb EPROM, demonstrating that this 0.8- mu m BiFAMOS is capable of sub-20-ns 4M EPROMs.<>
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