一种采用门调制自坍缩写辅助的10nm SRAM设计，使VMIN降低175mV，功耗可以忽略不计

2020 IEEE Symposium on VLSI Circuits Pub Date : 2020-06-01 DOI:10.1109/VLSICircuits18222.2020.9162782

Z. Guo, J. Wiedemer, Yusung Kim, P. S. Ramamoorthy, P. B. Sathyaprasad, Smita Shridharan, Daeyeon Kim, E. Karl

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引用次数: 1

摘要

提出了一种基于10nm CMOS技术，采用0.03667 um2 HCC位元的21Mb/mm2 SRAM设计。利用门调制自坍缩(GSC)写入辅助，以最小的能量开销使VMIN降低175mV。通过使用修改后的SRAM位元在基于行的配置中实现GSC电路，实例面积开销被限制在3-5%。

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A 10nm SRAM Design using Gate-Modulated Self-Collapse Write Assist Enabling 175mV VMIN Reduction with Negligible Power Overhead

A 21Mb/mm2 SRAM design using 0.0367um2 HCC bitcell on a 10nm CMOS technology is presented. Gate-modulated self-collapse (GSC) write assist is utilized to enable 175mV reduction in VMIN with minimal energy overhead. Instance area overhead is limited to 3–5% by implementing the GSC circuitry in a row-based configuration with modified SRAM bitcells.

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2020 IEEE Symposium on VLSI Circuits

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