基于EKV3.0的0.15/spl μ m CMOS技术的缩放问题

Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006. Pub Date : 2006-06-22 DOI:10.1109/MIXDES.2006.1706557

E. Kitonaki, A. Bazigos, M. Bucher, H. Puchner, S. Bhardwaj, Y. Papananos

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引用次数: 1

摘要

介绍了EKV3.0模型在0.15 μ m单多晶硅CMOS技术和埋道PMOS中的应用，重点介绍了该技术和模型的缩放特性。EKV3.0模型适合NMOS和PMOS在大温度范围内的弱、中、强反转漏极电流、跨导和输出特性。该技术和模型的缩放特性用与通道长度和宽度的拟合来说明。该模型还与实测的电容电压特性进行了比较。此外，还提供了与相同技术的BSIM3v3模型的一些比较

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Scaling Issues In An 0.15/spl mu/m CMOS Technology With EKV3.0

Application of the EKV3.0 model to 0.15mum CMOS technology with single poly, and buried channel PMOS, is presented with emphasis on scaling properties of the technology and the model. The EKV3.0 model is illustrated for its fit to NMOS and PMOS drain current, transconductances and output characteristics in weak, moderate and strong inversion over a large temperature range. Scaling properties of the technology and the model are illustrated with fits versus channel length and width. The model is also compared to measured capacitance-voltage characteristics. Furthermore, some comparisons to a BSIM3v3 model for the same technology are provided

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Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.

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