28nm FDSOI-Planar中SER的研究及与块体finet中SER的比较

2020 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2020-04-01 DOI:10.1109/IRPS45951.2020.9129644

T. Uemura, Byungjin Chung, J. Jo, Hai Jiang, Yongsung Ji, T. Jeong, R. Ranjan, Youngin Park, K. Hong, Seungbae Lee, H. Rhee, S. Pae, Euncheol Lee, Jaehee Choi, Shotaro Ohnishi, Ken Machida

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引用次数: 7

摘要

本文通过中子、α、质子和γ射线辐照测试，研究了28nm平面fdsoi技术中存储器和逻辑电路的软误差，并与块状finfet中的SER进行了比较。比较说明了平面fdsoi和块体finfet之间不同的SER趋势。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Investigating of SER in 28 nm FDSOI-Planar and Comparing with SER in Bulk-FinFET

This paper investigates soft error in memories and logic circuits in 28 nm planar-FDSOI technology by neutron, alpha, proton, and gamma-ray irradiation tests, and compares with SER in bulk-FinFET. The comparison elucidates the different SER trends between planar-FDSOI and bulk-FinFET.

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来源期刊

2020 IEEE International Reliability Physics Symposium (IRPS)

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