Acceleration of the TSDCE MIMO Channel Estimation Algorithm on a Multi-core Platform

The use of Multi-Processor System-on-Chip (MPSoC) is becoming widespread in a huge number of signal processing systems, including wireless communications and vehicular technology applications. In those scenarios, when Multiple-Input Multiple-Output (MIMO) communication schemes are considered, the system usually has to deal with a high number of communication links that involve sensors and antennas from different vehicles and users. The use of MIMO systems with a high number of antennas increases the complexity of many signal processing algorithms which could benefit from computationally efficient implementations. The Xilinx Zynq UltraScale+ EG Heterogeneous MPSoC is a well-positioned platform to manage computationally-demanding communication systems. This platform holds a dual-core ARM Cortex-R5, a quad-core ARM Cortex-A53, a graphics processing unit (GPU) and a high-end Field Programmable Gate Array (FPGA). In particular, this work aims to evaluate the computational performance of the Transformed Spatial Domain Channel Estimation (TSDCE), a novel millimeter-wave MIMO channel estimation algorithm, on the proposed embedded platform. This work focuses firstly on developing an efficient sequential implementation that runs on the ARM Cortex-A53, so that we can afterwards leverage the use of the multi-core system to accelerate the sequential performance.