Young-Ho Choi, Kihwan Seong, Byungsub Kim, J. Sim, Hong-June Park
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All-synthesizable 6Gbps voltage-mode transmitter for serial link
A high-speed transmitter for serial link interface was synthesized by using only Verilog codes and digital standard cells. The transmitter employs a differential voltage-mode architecture with a 2-tap feed-forward equalizer (FFE). A delay line which is locked to a data period is used for the FFE operation because a high speed flip-flop is not available in standard cells. The proposed transmitter chip in a 65nm CMOS process works at data rates up to 6Gbps with a 1.4m FR4 microstrip line of 20.6dB loss, occupies 0.0363mm2 and consumes 33.6mW at 1.2 V.
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