具有P/N混合栅极的超低待机电流ESD钳位MOSFET

2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD) Pub Date : 2016-09-01 DOI:10.1109/EOSESD.2016.7592554

K. Fukasaku, Daisuke Nakagawa, Toshihiko Miyazaki, T. Tatsumi, H. Ohnuma

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引用次数: 1

摘要

我们新的ESD设计方法使用栅极功函数控制和通道长度优化。我们开发了一种P/N混合栅极NMOS，其中通道区域的P栅极由于更高的v值而降低了亚阈值泄漏电流，重叠区域的N栅极由于较低的电场而降低了GIDL。

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Ultra-low standby current ESD clamp MOSFET with P/N hybrid gate

Our new ESD design methodology use gate work function control and channel length optimization. We developed a P/N hybrid gate NMOS, where P gate in the channel region reduces subthreshold leakage current thanks to a higher Vth, and N gate in the overlap region reduces GIDL thanks to a lower electric field.

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来源期刊

2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)

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