{"title":"高速数字传输倒装片互连特性研究","authors":"Chien-Chang Huang, Fang-Yi Lo, Wei-Che Lin","doi":"10.1109/APEMC.2015.7175391","DOIUrl":null,"url":null,"abstract":"This paper presents RF characterization of flip-chip interconnection in complementary-metal-oxide-semiconductor (CMOS) and glass-integrated-passive-device (GIPD) substrates by means of on-wafer scattering parameter (S-parameter) measurements, with high-speed digital transmission performance evaluations. The off-chip calibration is done firstly to shift the measured reference plane to the probe tips using the commercial impedance standard substrate (ISS) with line-reflect-match (LRM) method. Then the L-2L deembedding technique is applied for the two GIPD transmission lines to extract the RF characteristics of GIPD probe pads and transmission lines. Finally the designed thru-reflect-line (TRL) calibration standards in the CMOS chip are measured for resolving the flip-chip interconnection characteristics with the previous acquired GIPD parameters. The extracted data in two-port S-parameter are thereby simulated in time-domain to observe the high-speed digital transmission performance in eye-diagram representation. The shown result indicates the transmission speed in 40 Gbps works well in this flip-chip interconnection case.","PeriodicalId":325138,"journal":{"name":"2015 Asia-Pacific Symposium on Electromagnetic Compatibility (APEMC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Characterization of flip-chip interconnection for high speed digital transmission\",\"authors\":\"Chien-Chang Huang, Fang-Yi Lo, Wei-Che Lin\",\"doi\":\"10.1109/APEMC.2015.7175391\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents RF characterization of flip-chip interconnection in complementary-metal-oxide-semiconductor (CMOS) and glass-integrated-passive-device (GIPD) substrates by means of on-wafer scattering parameter (S-parameter) measurements, with high-speed digital transmission performance evaluations. The off-chip calibration is done firstly to shift the measured reference plane to the probe tips using the commercial impedance standard substrate (ISS) with line-reflect-match (LRM) method. Then the L-2L deembedding technique is applied for the two GIPD transmission lines to extract the RF characteristics of GIPD probe pads and transmission lines. Finally the designed thru-reflect-line (TRL) calibration standards in the CMOS chip are measured for resolving the flip-chip interconnection characteristics with the previous acquired GIPD parameters. The extracted data in two-port S-parameter are thereby simulated in time-domain to observe the high-speed digital transmission performance in eye-diagram representation. The shown result indicates the transmission speed in 40 Gbps works well in this flip-chip interconnection case.\",\"PeriodicalId\":325138,\"journal\":{\"name\":\"2015 Asia-Pacific Symposium on Electromagnetic Compatibility (APEMC)\",\"volume\":\"27 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-05-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 Asia-Pacific Symposium on Electromagnetic Compatibility (APEMC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/APEMC.2015.7175391\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 Asia-Pacific Symposium on Electromagnetic Compatibility (APEMC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APEMC.2015.7175391","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Characterization of flip-chip interconnection for high speed digital transmission
This paper presents RF characterization of flip-chip interconnection in complementary-metal-oxide-semiconductor (CMOS) and glass-integrated-passive-device (GIPD) substrates by means of on-wafer scattering parameter (S-parameter) measurements, with high-speed digital transmission performance evaluations. The off-chip calibration is done firstly to shift the measured reference plane to the probe tips using the commercial impedance standard substrate (ISS) with line-reflect-match (LRM) method. Then the L-2L deembedding technique is applied for the two GIPD transmission lines to extract the RF characteristics of GIPD probe pads and transmission lines. Finally the designed thru-reflect-line (TRL) calibration standards in the CMOS chip are measured for resolving the flip-chip interconnection characteristics with the previous acquired GIPD parameters. The extracted data in two-port S-parameter are thereby simulated in time-domain to observe the high-speed digital transmission performance in eye-diagram representation. The shown result indicates the transmission speed in 40 Gbps works well in this flip-chip interconnection case.