{"title":"基于fpga的二维离散余弦变换实现","authors":"H.B. Helal, A. Salama, S. Mashali","doi":"10.1109/NRSC.1999.760887","DOIUrl":null,"url":null,"abstract":"A new algorithm for the computation of a 2-D DCT is presented, the computational complexity as measured in terms of the number of multiplications and additions is kept to a minimum, the algorithm is amenable to implementation using field programmable gate arrays (FPGAs). An example of a 4/spl times/4 2-D DCT is presented, and its performance is evaluated.","PeriodicalId":250544,"journal":{"name":"Proceedings of the Sixteenth National Radio Science Conference. NRSC'99 (IEEE Cat. No.99EX249)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Realization of FPGA-based two dimensional discrete cosine transform\",\"authors\":\"H.B. Helal, A. Salama, S. Mashali\",\"doi\":\"10.1109/NRSC.1999.760887\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new algorithm for the computation of a 2-D DCT is presented, the computational complexity as measured in terms of the number of multiplications and additions is kept to a minimum, the algorithm is amenable to implementation using field programmable gate arrays (FPGAs). An example of a 4/spl times/4 2-D DCT is presented, and its performance is evaluated.\",\"PeriodicalId\":250544,\"journal\":{\"name\":\"Proceedings of the Sixteenth National Radio Science Conference. NRSC'99 (IEEE Cat. No.99EX249)\",\"volume\":\"24 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-02-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the Sixteenth National Radio Science Conference. NRSC'99 (IEEE Cat. No.99EX249)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NRSC.1999.760887\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the Sixteenth National Radio Science Conference. NRSC'99 (IEEE Cat. No.99EX249)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NRSC.1999.760887","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Realization of FPGA-based two dimensional discrete cosine transform
A new algorithm for the computation of a 2-D DCT is presented, the computational complexity as measured in terms of the number of multiplications and additions is kept to a minimum, the algorithm is amenable to implementation using field programmable gate arrays (FPGAs). An example of a 4/spl times/4 2-D DCT is presented, and its performance is evaluated.