采用四分之一微米相移光刻技术的256 Mbit dram的0.72 μ m/sup /嵌入式STC (RSTC)技术

1992 Symposium on VLSI Technology Digest of Technical Papers Pub Date : 1992-06-02 DOI:10.1109/VLSIT.1992.200618

K. Sagara, T. Kure, S. Shukuri, J. Yugami, N. Hasegawa, H. Shinriki, H. Goto, H. Yamashita, E. Takeda

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引用次数: 8

摘要

提出了一种既能实现精细图形描绘又能实现高电池电容的嵌入式堆叠电容器结构。采用RSTC结构，制作了0.25 μ m相移光刻和CVD-W板技术的实验存储阵列。在0.72 μ m/sup 2/ cell的条件下，获得了25-fF/cell的电容。

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A 0.72 mu m/sup 2/ recessed STC (RSTC) technology for 256 Mbit DRAMs using quarter-micron phase-shift lithography

A recessed stacked capacitor (RSTC) structure to achieve both fine-pattern delineation and high cell capacitance is presented. Using a RSTC structure, an experimental memory array with 0.25 mu m phase-shift lithography and CVD-W plate technology has been fabricated. A 25-fF/cell capacitance was obtained in a 0.72 mu m/sup 2/ cell.<>

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1992 Symposium on VLSI Technology Digest of Technical Papers

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