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引用次数: 2
摘要
提出了一种新的乘二增益级(MBT-GS)(/ sp1倍/2)，该增益级抑制了电容失配对增益的敏感性。在三相中使用一个运算放大器(运放)，可以获得2个增益，而不受电容之间不匹配的影响。本文对该结构进行了分析研究，并在HSPICE中使用通用的0.6 /spl μ m CMOS技术进行了蒙特卡罗模拟。仿真结果清楚地表明，新体系结构降低了匹配需求。
A new multiply-by-two gain-stage with enhanced immunity to capacitor-mismatch
A new multiply-by-two gain-stage (MBT-GS)(/spl times/2) is presented in which the gain-sensitivity to the capacitors' mismatches is suppressed. Using one operational amplifier (op-amp) in three phases, a gain of two, which is not highly influenced by the mismatches between the capacitors, is achieved. An analytical study of the architecture is presented followed by some Monte-Carlo simulations using a generic 0.6 /spl mu/m CMOS technology in HSPICE. Simulations clearly show the reduction of the matching-requirements in the new architecture.
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