{"title":"用于高端/高清电视接收机的单片2fH上变频","authors":"C. Correa, T. Christopher, T. Saeger","doi":"10.1109/ICCE.1995.517886","DOIUrl":null,"url":null,"abstract":"Presents a description of a one-chip up-converter architecture study, which performs a 1fH to 2fH, line-doubling, video up-conversion, for both 50 Hz-625 lines and 60 Hz-525 lines video systems. This architecture concept, the DMU (dual mode up-converter), converts the interlaced digital YUV video input signals into either a non-interlaced progressive 1 V field rate (50 Hz/60 Hz) or a interlaced doubled 2 V field rate (100 Hz/120 Hz) display format.","PeriodicalId":306595,"journal":{"name":"Proceedings of International Conference on Consumer Electronics","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"1995-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"One chip 2fH up-converter for high end/HDTV TV receivers\",\"authors\":\"C. Correa, T. Christopher, T. Saeger\",\"doi\":\"10.1109/ICCE.1995.517886\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Presents a description of a one-chip up-converter architecture study, which performs a 1fH to 2fH, line-doubling, video up-conversion, for both 50 Hz-625 lines and 60 Hz-525 lines video systems. This architecture concept, the DMU (dual mode up-converter), converts the interlaced digital YUV video input signals into either a non-interlaced progressive 1 V field rate (50 Hz/60 Hz) or a interlaced doubled 2 V field rate (100 Hz/120 Hz) display format.\",\"PeriodicalId\":306595,\"journal\":{\"name\":\"Proceedings of International Conference on Consumer Electronics\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-06-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of International Conference on Consumer Electronics\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCE.1995.517886\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of International Conference on Consumer Electronics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCE.1995.517886","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
One chip 2fH up-converter for high end/HDTV TV receivers
Presents a description of a one-chip up-converter architecture study, which performs a 1fH to 2fH, line-doubling, video up-conversion, for both 50 Hz-625 lines and 60 Hz-525 lines video systems. This architecture concept, the DMU (dual mode up-converter), converts the interlaced digital YUV video input signals into either a non-interlaced progressive 1 V field rate (50 Hz/60 Hz) or a interlaced doubled 2 V field rate (100 Hz/120 Hz) display format.
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